Studies of two-dimensional materials using electrons: reflectivity, tunneling and transport

Discussion
Date:
Th, 01.06.2017 18:30  –   Th, 01.06.2017 19:30
Speaker:
Prof. Dr. Randall M. Feenstra
Address:
Magnus-Haus Berlin
Am Kupfergraben 7, 10117 Berlin, Germany

Language:
English
Event partner:
Wilhelm und Else Heraeus-Stiftung
Contact person:
Andreas Böttcher,
DPG Association:
Physikalische Gesellschaft zu Berlin e. V., Regionalverband Berlin/Brandenburg der Deutschen Physikalischen Gesellschaft e. V. (PGzB)  

Description

Moderation: Holger Eisele, Technische Universität Berlin


Berliner Physikalisches Kolloquium
im Magnus-Haus, Am Kupfergraben 7, 10117 Berlin
Eine gemeinsame Veranstaltung der Physikalischen Gesellschaft zu Berlin e.V.,
der Freien Universität Berlin, der Humboldt-Universität zu Berlin,
der Technischen Universität Berlin und der Universität Potsdam
‒ gefördert durch die Wilhelm und Else Heraeus-Stiftung

Zusammenfassung
Over the past decade, much research world-wide has focused on two-dimensional (2D) materials, in which the electrons are localized within a single atomic plane. Obtaining μm-size flakes of 2D material by "exfoliating" (peeling apart) layers using adhesive tape has been a standard practice for decades, but only recently has this method been applied to produce small, microfabricated electronic devices on the flakes (Geim and Novoselov, Nobel Prize 2010). However, for practical electronics of the future, such devices must be produced on grown (deposited), large-area 2D layers, rather than with flakes. In this talk, studies of the structure of grown 2D layers will be described. The methods of low-energy electron microscopy and low-temperature scanning tunneling microscopy are used to obtain detailed, atomic-scale views of the structure of the layers. The end goal of the studies is for fabrication of interlayer tunneling field-effect transistors (TFETs). Simulations of such structures are shown to yield current magnitudes that are useful for applications, and experimental progress in fabricating interlayer TFETs will be discussed.

Kolloquium_20170601.pdf